Tyler
05-02-2005, 01:42 PM
On the transistor design level, improvements have been made by straining the silicon to physically alter the lattice geometry and thereby optimizing the conductivity between source and drain. Starting out with a relatively simple Silicon-Germanium epitaxy, we are looking at uniaxial compression and stretching for PMOS and NMOS devices, respectively, to speed up the currents and reduce power consumption at the same time.
More at LostCircuits. (http://www.lostcircuits.com/cpu/amd_venice/)
More at LostCircuits. (http://www.lostcircuits.com/cpu/amd_venice/)