Memory Timings Analysis

[Keefe]

Harry has prepared a memory timings analysis article, using Crucial's PC2700 DDR RAM as a reference.

It's generally known that smaller and more aggressive timings combined with higher clock speeds leads to higher performance, but for the most part, the increase in performance from tweaking each individual setting is relatively unknown. Perhaps in a bit too ambitious move, I set out to examine the impact of each individual memory timing and clock speed on overall performance.

Click here to read the the full review.

As usual, the world is not that simple and Real World (TM) performance depends on more
than plain memory bandwidth. If you had tried a more diverse set of permance messurements,
notably a pointer chasing loop, you'd have observed something quite different: a low CAS latency can be more important than higher memory clock.

CL2 @ 166MHz = 12ns
CL1.5 @ 100MHz = 15ns
CL2 @ 133MHz = 15ns
CL3 @ 166MHz = 18ns
CL2 @ 100MHz = 20ns
CL3 @ 133MHz = 22ns

The discrete CL (CAS latency in cycles) is derived from the real continous-time latency
constraints, so the optimal CL and CLK setting depends on how close you can get.
For example, that constraint is 14ns, clearly you're better off going with CL2@133MHz than
with CL3@166MHz FROM A LATENCY PERSPECTIVE. For bandwidth, that latter is better. The optimum choise depends on the benchmark.

/Tommy

I'd have to agree that changing latency settings and then measuring bandwidth is kinda a bogus test - to first order, the bandwidth shouldn't change at ALL. You might as well just measure bogomips

What would be interesting is to benchmark using something doing a bit more real-world calculations. Even prime95 or another scientific application might be more informing...