AMD Athlon64 "Venice"

[Tyler]

On the transistor design level, improvements have been made by straining the silicon to physically alter the lattice geometry and thereby optimizing the conductivity between source and drain. Starting out with a relatively simple Silicon-Germanium epitaxy, we are looking at uniaxial compression and stretching for PMOS and NMOS devices, respectively, to speed up the currents and reduce power consumption at the same time.

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