DDR-II is expected to offer a minimum bandwidth of 400 Mbits/second per pin based on 100-MHz signaling. With chip frequencies rising, a 150-MHz core could produce bandwidth as high as 600 Mbits/s per pin. The interface is expected to run at 1.8 volts, down from the 2.5 V of DDR-I, and it will demand new packaging at both the chip and module levels, as well as a new data-capture and synchronization scheme.
The first spin of DDR technology doubled the performance of standard synchronous DRAM by pumping data bits on both the rising and falling edge of the clock cycle. DDRII doubles the total bandwidth again by increasing the data fetch from 2 to 4 bits. As a result, the same 100-MHz SDRAM core that became a 200-Mbit/s-per-pin DDR device will jump to 400 Mbits/s per pin with DDR-II.
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